一、二选一数据选择器
1.模块框图
2.逻辑功能
①当sel为0时,y输出a和b的与;
②当sel为1时,y输出a和b的异或;
3.verilog设计代码
①使用assign语句实现组合逻辑
module Select2_1( input a,b,sel, output y ); assign y = sel?(a^b):(a&b); endmodule
②使用always语句块实现组合逻辑 (always语句块中被赋值的变量必须为reg型)
//Use always statement module Select2_1( input a,b,sel, output reg y ); always @(a or b or sel) begin if (sel) begin y <= a^b; end else begin y <= a&b; end end endmodule
4.测试仿真代码
//testbench of the Select2_1 `timescale 1ns/10ps module Select2_1_testbench(); reg A,B,SEL; wire Y; //instantiation the module Select2_1 U1( .a(A), .b(B), .sel(SEL), .y(Y) ); initial begin #0 A <= 0; B <= 0; SEL <= 0; #10 A <= 1; B <= 0; SEL <= 0; #10 A <= 1; B <= 1; SEL <= 0; #10 A <= 0; B <= 1; SEL <= 0; #10 A <= 1; B <= 0; SEL <= 1; #10 A <= 1; B <= 1; SEL <= 1; #10 A <= 0; B <= 1; SEL <= 1; #10 $stop; end endmodule
5.测试仿真结果
二、多路选择器
1.模块框图
2.逻辑功能
①当sel为00时,y是a和b的与;
②当sel为01时,y是a和b的或;
③当sel为10时,y是a和b的异或;
④当sel为11时,y是a和b的同或;
3.verilog代码设计
//use case statement module MUX4_1( input A,B, input [1:0] SEL, output reg Y ); always @(A or B or SEL) begin case (SEL) 2'b00 : begin Y <= A&B; end 2'b01 : begin Y <= A|B; end 2'b10 : begin Y <= A^B; end 2'b11 : begin Y <= ~(A^B); end endcase end endmodule
4.测试仿真代码
//testbench of the MUX4_1 `timescale 1ns/10ps module MUX4_1_testbench(); reg a,b; reg [1:0] sel; wire y; //instantiation the MUX4_1 module MUX4_1 U1( .A(a), .B(b), .SEL(sel), .Y(y) ); initial begin #0 a <= 0; b <= 0; sel <= 2'b00; #10 a <= 1; b <= 0; sel <= 2'b01; #10 a <= 1; b <= 1; sel <= 2'b10; #10 a <= 0; b <= 1; sel <= 2'b11; #10 a <= 1; b <= 0; sel <= 2'b10; #10 a <= 1; b <= 1; sel <= 2'b00; #10 a <= 0; b <= 1; sel <= 2'b10; #10 $stop; end endmodule
5.仿真结果