参考文章：

Linux下VCS与Verdi联合仿真简易教程及例子示范 - 灰信网（软件开发博客聚合）https://www.freesion.com/article/71471173457/这个文章的内容较为全面，但是有些许的不足，将发生的更改记录下来

1、

vcs -R -full64 +v2k -fsdb +define+FSDB -sverilog counter.v tb_counter.v timescale.v -l run.log

在进行上述操作的时候，如果出现以下问题

Top Level Modules:
       counter_tb
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module counter_tb
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  -rdynamic  -Wl,-rpath=/usr/synopsys/vcs/O-2018.09-SP2/linux64/lib -L/usr/synopsys/vcs/O-2018.09-SP2/linux64/lib   objs/amcQw_d.o   _16329_archive_1.so  SIM_l.o       rmapats_mop.o rmapats.o rmar.o rmar_nd.o  rmar_llvm_0_1.o rmar_llvm_0_0.o          -lnuma -lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs    -lvcsnew -lsimprofile -luclinative /usr/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_tls.o   -Wl,-whole-archive -lvcsucli -Wl,-no-whole-archive        _vcs_pli_stub_.o   /usr/synopsys/vcs/O-2018.09-SP2/linux64/lib/vcs_save_restore_new.o /usr/synopsys/verdi/Verdi_O-2018.09-SP2/share/PLI/VCS/LINUX64/pli.a -ldl  -lc -lm -lpthread -ldl
ld: cannot find crtbegin.o: No such file or directory
make: *** [product_timestamp] Error 1
Make exited with status 2
CPU time: .529 seconds to compile + .408 seconds to elab + .550 seconds to link

则是由于centos的gcc版本问题，只要升级gcc版本即可