Implement the following circuit:
Note that this is a latch, so a Quartus warning about having inferred a latch is expected.
module top_module ( input d, input ena, output q); always@(*) begin if(ena) q <= d; end endmodule
module top_module ( input clk, input in, output out); always@(posedge clk) begin out<= out ^in; end endmodule
module top_module ( input clk, input w, R, E, L, output reg Q ); wire mid_a; wire mid_b; assign mid_b = L ? R :mid_a; assign mid_a = E ? w :Q; always@(posedge clk) begin Q <= mid_b; end endmodule
module top_module ( input clk, input x, output z ); reg a,b,c; wire D_a,D_b,D_c; assign D_a = x ^a; assign D_b = x & (!b); assign D_c = x | (!c); assign z = !(a|b|c); always @(posedge clk) begin a <= D_a; b <= D_b; c <= D_c; end endmodule